SWITCH 300-115 1.0 Layer 2 Technologies

physical switching

1. CPU
2. interface asic (application specific integrated circuit)
3. memory – cpu and iomem memory accessible by interface asics

process switching

1. packet ingresses interface
2. ingress asic ships packet to iomem and interrupts cpu
3. cpu copies packet from iomem to main memory
4. ios route process looks up route table for egress interface
5. l3 and l2 headers are modified and the packet gets shipped to the egress interface output queue
6. egress asic ships packet

fast switching

1. packet ingresses interface
2. ingress asic ships packet to iomem and interrupts cpu
3. cpu copies packet from iomem to main memory
4. ios checks for cache entry, if exists, applies l3 and ls information.  if not exists, route process is called and result is put into fast cache
5. l3 and l2 headers are modified and the packet gets shipped to the egress interface output queue
6. egress asic ships packet

cef switching

1. packet ingresses interface
2. ingress asic ships packet to iomem, does fib lookup and gets next ho from adjacency table
3. if cef switchable, replace l3 and l2 header with adjacency table header.  if not cef’able, go to fast or process switching
4. iomem area containing packet is linked to egress asic
5. egress asic ships packet